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regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein.
preliminary: the specification of this device are subject to change without notice. please contact your nearest hitachi? sales dept. regarding specification. hm62g18512a series 9m synchronous fast static ram (512k-word 18-bit) ade-203-1268b (z) preliminary rev. 0.2 sep. 12, 2001 description the hm62g18512a is a synchronous fast static ram organized as 512-kword 18-bit. it has realized high speed access time by employing the most advanced cmos process and high speed circuit designing technology. it is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. it is packaged in standard 119- bump bga. note: all power supply and ground pins must be connected for proper operation of the device. features 2.5 v 5% and 3.3 v 5% operation and 0.9 v (v ref ) internal self-timed late write byte write control (2 byte write selects, one for each 9-bit) optional 36 configuration hstl compatible i/o programmable impedance output drivers user selective input trip-point differential, hstl clock inputs asynchronous g output control asynchronous sleep mode limited set of boundary scan jtag ieee 1149.1 compatible protocol: single clock register-register mode
hm62g18512a series 2 ordering information type no. access time cycle time package HM62G18512ABP-30 hm62g18512abp-33 hm62g18512abp-40 1.7 ns 1.7 ns 2.0 ns 3.0 ns 3.3 ns 4.0 ns 119-bump 1. 27 mm 14 mm 22 mm bga (bp-119c) pin arrangement 12 34567 av ddq sa0 sa1 nc sa13 sa12 v ddq b nc nc sa2 nc sa14 sa11 nc c nc sa3 sa4 v dd sa5 sa6 nc d dqb5 nc v ss zq v ss dqa0 nc e nc dqb3 v ss ss v ss nc dqa4 fv ddq nc v ss g v ss dqa1 v ddq g nc dqb6 sweb nc v ss nc dqa8 h dqb7 nc v ss nc v ss dqa2 nc jv ddq v dd v ref v dd v ref v dd v ddq k nc dqb2 v ss kv ss nc dqa7 l dqb8 nc v ss k swea dqa6 nc mv ddq dqb1 v ss swe v ss nc v ddq n dqb4 nc v ss sa8 v ss dqa3 nc p nc dqb0 v ss sa10 v ss nc dqa5 r nc sa7 m1 v dd m2 sa15 nc t nc sa18 sa9 nc sa17 sa16 zz uv ddq tms tdi tck tdo nc v ddq (top view)
hm62g18512a series 3 pin description name i/o type descriptions notes v dd supply core power supply v ss supply ground v ddq supply output power supply v ref supply input reference: provides input reference voltage k input clock input. active high. k input clock input. active low. ss input synchronous chip select swe input synchronous write enable san input synchronous address input n = 0-18 swex input synchronous byte write enables x = a, b g input asynchronous output enable zz input power down mode select zq input output impedance control 1 dqxn i/o synchronous data input/output x = a, b n = 0, 1, 2...8 m1, m2 input output protocol mode select tms input boundary scan test mode select tck input boundary scan test clock tdi input boundary scan test data input tdo output boundary scan test data output nc no connection m1 m2 protocol notes v ss v dd synchronous register to register operation 2 notes: 1. zq is to be connected to v ss via a resistance rq where 225 w rq 275 w . if zq = v ddq or open, output buffer impedance will be maximum. 2. there is 1 protocol with mode pin. for this application, m1 and m2 need to connect to v ss and v dd , respectively. the state of the mode control inputs must be set before power-up and must not change during device operation. mode control inputs are not standard inputs and may not meet v ih or v il specification. this sram is tested only in the synchronous register to register operation.
hm62g18512a series 4 block diagram a0 to a18 jtag register jtag register jtag register jtag register jtag register jtag register jtag register jtag register jtag register jtag tap controller r-add register ss register swe register swex register w-add register ss swe swex g zz v ref zq tdi tck tms tdo dqa0-8 dqb0-8 k k mux row decoder multiplex 19 2 18 2 19 19 1 wrc doc d-out register ob d-in register wa sa match column decoder memory cell array (512k 18) clk control impedance contorol logic
hm62g18512a series 5 operation table zz ss g swe swea sweb k k operation dq (n) dq (n + 1) h sleep mode high-z high-z lh l-h h-l dead (not selected) high-z l h dead (dummy read) high-z high-z ll lh l-h h-l read dout (a,b)0-8 ll l l l l-h h-l write a, b byte high-z din (a,b)0-8 ll l l h l-h h-l write a byte high-z din (a)0-8 ll l h l l-h h-l write b byte high-z din (b)0-8 notes: 1. means don? care for synchronous inputs, and h or l for asynchronous inputs. 2. swe , ss , swea to sweb , sa are sampled at the rising edge of k clock. 3. although differential clock operation is implied, this sram will operate properly with one clock phase (either k or k ) tied to v ref . under such single-ended clock operation, all parameters specified within this document will be met.
hm62g18512a series 6 absolute maximum ratings parameter symbol value unit notes input voltage on any pin v in ?.5 to v ddq + 0.5 v 1, 4 core supply voltage v dd ?.5 to 3.9 v 1 output supply voltage v ddq ?.5 to 2.2 v 1, 4 operating temperature t opr 0 to 70 c storage temperature t stg ?5 to 125 c output short?ircuit current i out 25 ma latch up current i li 200 ma package junction to case thermal resistance q jc 2 c/w 5, 7 package junction to ball thermal resistance q jb 5 c/w 6, 7 notes: 1. all voltage is referred to v ss . 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted the operation conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. these cmos memory circuits have been designed to meet the dc and ac specifications shown in the tables after thermal equilibrium has been established. 4. the following supply voltage application sequence is recommended: v ss , v dd , v ddq , v ref then vin. remember, according to the absolute maximum ratings table, v ddq is not exceed 2.2 v, whatever the instantaneous value of v ddq . 5. q jc is measured at the center of mold surface in fluorocarbon (see figure ?efinition of measurement?. 6. q jb is measured on the center ball pad after removing the ball in fluorocarbon (see figure ?efinition of measurement?. 7. these thermal resistance values have error of 5 c/w. q jc t. c. fluorocarbon q jb fluorocarbon t. c. definition of measurement
hm62g18512a series 7 note: the following the dc and ac specifications shown in the tables, this device is tested under the minimum transverse air flow exceeding 500 linear feet per minute. dc operating conditions (ta = 0 to 70 c) parameter symbol min typ max unit notes supply voltage (core) v dd 2.38 2.5 2.63 v 2.5 v part v dd 3.14 3.3 3.47 v 3.3 v part supply voltage (i/o) v ddq 1.6 1.8 2.0 v input reference voltage (i/o) v ref 0.8 0.9 1.0 v 1 input high voltage v ih v ref + 0.1 v ddq + 0.3 v input low voltage v il ?.3 v ref ?0.1 v clock differential voltage v dif 0.1 v ddq + 0.3 v 2, 3 clock common mode voltage v cm 0.6 0.90 v 3 notes: 1. peak to peak ac component superimposed on v ref may not exceed 5% of v ref . 2. minimum differential input voltage required for differential input clock operation. 3. see following figure. v ddq v ss v dif v cm differential voltage/common mode voltage
hm62g18512a series 8 dc characteristics (ta = 0 to 70 c, v dd = 2.5 v 5%, 3.3 v 5%) parameter symbol min typ max unit notes input leakage current i li 2 m a1 output leakage current i lo 5 m a2 standby current i sbzz 100 ma 3 v dd operating current, excluding output drivers 4 ns cycle i dd4 400 ma 4 v dd operating current, excluding output drivers 3 ns and 3.3 ns cycle i dd3 500 ma 4 quiescent active power supply current i dd2 200 ma 5 maximum power dissipation, including output data p 2.3 at 2.5 v part w 6 2.8 at 3.3 v part w 6 output low voltage (programmable impedance mode) v ol1 v ss ? ddq/2 v output high voltage (programmable impedance mode) v oh1 v ddq/2 ? ddq v output low voltage v ol2 v ss ? ss + 0.4 v 7 output high voltage v oh2 v ddq ?0.4 v ddq v8 zq pin connect resistance rq 225 250 275 w output low current i ol (v ddq /2)/ [{(rq/5 ?5 w )}-15%] ?v ddq /2)/ [{(rq/5 ?5 w )}+15%] ma 9, 11, 12 output high current i oh (v ddq /2)/ [{(rq/5 ?5 w )} +15%] ?v ddq /2)/ [{(rq/5 ?5 w )}-15%] ma 10, 11, 12 notes: 1. 0 vin v ddq for all input pins (except v ref , zq, m1, m2 pin). 2. 0 vout v ddq , dq in high-z. 3. all inputs (except clock) are held at either v ih or v il , zz is held at v ih , iout = 0 ma. spec is guaranteed at 75 c junction temperature. 4. iout = 0 ma, read 50%/write 50%, v dd = v dd max, v in = v ih or v il , frequency = minimum cycle. 5 . iout = 0 ma, read 50%/write 50%, v dd = v dd max, v in = v ih or v il , frequency = 3 mhz. 6. output drives a 12pf load and switches every cycle. this parameter should be used by the sram designer to determine electrical and package requirements for the sram device. 7. i ol = 6 ma (rq = 175 w ). 8. i oh = ? ma (rq = 175 w ). 9. v ol = 1/2 v ddq . 10. v oh = 1/2 v ddq . 11. parameter tested with rq = 250 w and v ddq = 1.8 v.
hm62g18512a series 9 12. output buffer impedance can be programmed by terminating the zq pin to v ss through a precision resister (rq). the value of rq is five times the output impedance desired. the allowable range of rq to guarantee impedance matching with a tolerance of 15% is 250 typical . if the status of zq pin is open, output impedance is maximum. maximum impedance occurs with zq connected to v ddq . the impedance update of the output driver occurs when the sram is in high-z. write and deselect operations will synchronously switch the sram into and out of high- z, therefore triggering an update. the user may choose to invoke asynchronous g updates by providing a g setup and hold about the k clock to guarantee the proper update. at power-up, the output impedance defaults to minimum impedance. it will take 1024 cycles for the impedance to be completely updated if the programmed impedance is much higher than minimum impedance. the total external capacitance of zq pin must be less than 7.5 pf. capacitance (ta = 25 c, f = 1 mhz) parameter symbol min max unit note input capacitance (san, ss , swe , swex )c in 4 pf 1 input capacitance (k, k , g )c clk 5 pf 1 input/output capacitance (dqxn) c io 5 pf 1 note: 1. this parameter is sampled and not 100% tested. ac characteristics (ta = 0 to 70 c, v dd = 2.5 v 5% and 3.3 v 5%) test conditions input pulse levels (k, k ): v dif = 0.75 v, v cm = 0.9 v input timing reference level (k, k ): differential cross point input pulse levels (except k, k ): v il = 0.3 v, v ih = 1.5 v input and output timing reference levels (except k, k ): v ref = 0.9 v input rise and fall time: 0.5 ns (10% to 90%) output load: see figure parameters are tested with rq = 250 w and v ddq = 1.8 v 50 w 16.7 w 16.7 w 50 w 5 pf dq 0.9 v 50 w 16.7 w 50 w 5 pf 0.9 v 0.9 v
hm62g18512a series 10 ac characteristics (ta = 0 to 70 c, v dd = 2.5 v 5% and 3.3 v 5%) single differential clock register-register mode (m1 = v ss , m2 = v dd ) hm62g18512a -30 -33 -40 parameter symbol min max min max min max unit notes ck clock cycle time t khkh 3.0 3.3 4.0 ns ck clock high width t khkl 1.2 1.3 1.5 ns ck clock low width t klkh 1.2 1.3 1.5 ns address setup time t avkh 0.5 0.5 0.5 ns 2 data setup time t dvkh 0.5 0.5 0.5 ns 2 address hold time t khax 0.5 0.5 0.5 ns 2 data hold time t khdx 0.5 0.5 0.5 ns 2 clock high to output valid t khqv 1.7 1.7 2.0 ns 1 clock high to output hold t khqx 0.5 0.5 0.5 ns 1, 2 clock high to output low-z ( ss control) t khqx2 0.5 0.5 0.5 ns 1, 5 clock high to output high-z t khqz 2.0 2.0 2.0 ns 1, 3 output enable low to output low-z t glqx 0.3 0.3 0.3 ns 1, 2, 5 output enable low to output valid t glqv 1.7 1.7 2.0 ns 1, 3 output enable low to output high-z t ghqz 1.5 1.5 1.5 ns 1, 3 sleep mode recovery time t zzr 10.0 10.0 10.0 ns 6 sleep mode enable time t zze 9.0 9.0 9.0 ns 1, 3, 6 notes: 1. see ac test loading figure. 2. parameter is guaranteed by design. 3. transitions are measured at start point of output high impedance from output low impedance. 4. output driver impedance update specifications for g induced updates. write and deselected cycles will also induce output driver updates during high-z. 5. transitions are measured 200 mv from steady state voltage. 6. when zz is switching, clock input k must be at same logic levels for reliable operation.
hm62g18512a series 11 timing waveforms read cycle-1 k k sa a1 a2 a3 a4 ss swe swex dq do 1 do 0 do 2 t khkh t avkh t khax t avkh t khax t avkh t khax t khqx t khqv t khkl t klkh note: g , zz = v il
hm62g18512a series 12 read cycle-2 ( ss controlled) k k sa ss swe swex dq do 0 do 1 do 3 t khkh t klkh t avkh t avkh t khax t khax t avkh t khax t khkl a1 a3 a4 t khqz t khqx2 note: g , zz = v il
hm62g18512a series 13 read cycle-3 ( g controlled) k k sa a1 a2 a3 a4 ss swe swex g dq do 1 do 0 do 3 t khkh t avkh t khax t avkh t khax t ghqz t glqv t glqx t avkh t khax t klkh t khkl note: zz = v il
hm62g18512a series 14 write cycle k k sa ss swe swex dq di 0 di 1 di 2 di 3 g t khkh t avkh t khax t avkh t khax t avkh t khax t avkh t khax t dvkh t khdx t klkh t khkl a1 a2 a3 a4 note: zz = v il
hm62g18512a series 15 read-write cycle read write read ( g control) read dead ( ss control) write a7 a6 a4 a3 a1 t avkh t avkh t khax t avkh t khax t ghqz t dvkh t khdx t glqx t glqv t khqx t khqv t khqz do 0 do 1 do 4 di 3 di 6 t avkh t khax t khax k k sa ss swe swex g dq note: zz = v il t khkh t khkl t klkh zz control a1 do 1 sleep active sleep active sleep off t avkh t khax t avkh t khax k k sa ss swe swex zz dq note: g = v il t khkh t zzr t zze t khkl t klkh
hm62g18512a series 16 boundary scan test access port operations in order to perform the interconnect testing of the modules that include this sram, the serial boundary scan test access port (tap) is designed to operate in a manner consistent with ieee standard 1149.1 - 1990. but does not implement all of the functions required for 1149.1 compliance the hm62g series contains a tap controller. instruction register, boundary scans register, bypass register and id register. test access port pins symbol i/o name tck test clock tms test mode select tdi test data in tdo test data out note: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. to disable the tap, tck must be connected to v ss . tdo should be left unconnected. to test boundary scan, zz pin need to be kept below v ref ?0.4 v. tap dc operating conditions (ta = 0 to 70 c) parameter symbol min max unit notes boundary scan input high voltage v ih 2.0 3.6 v boundary scan input low voltage v il ?.3 0.8 v boundary scan input leakage current i li ? 5 m a1 boundary scan output low voltage v ol 0.4 v 2 boundary scan output high voltage v oh 2.4 v 3 notes: 1. 0 vin v dd for all logic input pin. 2. i ol = 8 ma at v dd = 3.3 v. 3. i oh = ? ma at v dd = 3.3 v.
hm62g18512a series 17 tap ac characteristics (ta = 0 to 70 c) parameter symbol min max unit note test clock cycle time t thth 67 ns test clock high pulse width t thtl 30 ns test clock low pulse width t tlth 30 ns test mode select setup t mvth 10 ns test mode select hold t thmx 10 ns capture setup t cs 10 ns 1 capture hold t ch 10 ns 1 tdi valid to tck high t dvth 10 ns tck high to tdi don? care t thdx 10 ns tck low to tdo unknown t tlqx 0ns tck low to tdo valid t tlqv ?0ns note: 1. t cs + t ch defines the minimum pause in ram i/o pad transitions to assure pad data capture. tap test conditions (v dd = 3.3 v) tempreture: 0 c ta 70 c input timing measurement reference level: 1.5 v input pulse levels: 0 to 3.0 v input rise and fall time: 2.0 ns typical (10% to 90%) output timing measurement reference level: 1.5 v test load termination supply voltage (v t ): 1.5 v output load: see figures v t = 1.5 v 50 w z 0 = 50 w dut tdo
hm62g18512a series 18 tap controller timing diagram tck tms tdi tdo ram address t thth t thtl t tlth t mvth t thmx t thdx t dvth t tlqv t tlqx t cs t ch test access port registers register name length symbol note instruction register 3 bits ir [0;2] bypass register 1 bit bp id register 32 bits id [0;31] boundary scan register 51 bits bs [1;51]
hm62g18512a series 19 tap controller instruction set ir2 ir1 ir0 instruction operation 0 0 0 sample-z tristate all data drivers and capture the pad value 0 0 1 idcode 0 1 0 sample-z tristate all data drivers and capture the pad value 0 1 1 bypass 1 0 0 sample 1 0 1 bypass 1 1 0 bypass 1 1 1 bypass note: this device does not perform extest, intest or the preload portion of the preload command in ieee 1149.1.
hm62g18512a series 20 boundary scan order bit no. bump id signal name bit no. bump id signal name 15rm2272bnc 26tsa283asa 34psa293csa 4 6rsa30 2csa 55tsa312asa 6 7t zz 32 1d dqb 7 7p dqa 33 2e dqb 8 6n dqa 34 2g dqb 9 6l dqa 35 1h dqb 10 7k dqa 36 3g sweb 11 5l swea 37 4d zq 12 4l k 38 4e ss 13 4k k 39 4g nc 14 4f g 40 4h nc 15 6h dqa 41 4m swe 16 7g dqa 42 2k dqb 17 6f dqa 43 1l dqb 18 7e dqa 44 2m dqb 19 6d dqa 45 1n dqb 20 6a sa 46 2p dqb 21 6c sa 47 3t sa 22 5c sa 48 2r sa 23 5a sa 49 4n sa 24 6b sa 50 2t sa 25 5b sa 51 3r m1 26 3b sa notes: 1. bit#1 is the first scan bit to exit the chip. 2. the nc pads listed in this table are indeed no connects, but are represented in the boundary scan register by a ?lace holder? placeholder registers are internally connected to v ss . 3. in boundary scan mode, differential input k and k are referenced to each other and must be at opposite logic levels for reliable operation. 4. zz must remain at v il during boundary scan. 5. in boundary scan mode, zq must be driven to v ddq or v ss supply rail to ensure consistent results. 6. m1 and m2 must be driven to v dd or v ss supply rail to ensure consistent results.
hm62g18512a series 21 id register part revision number (31:28) device density and configuration (27:18) vendor definition (17:12) vendor jedec code (11:1) smart bit (0) hm62g18512a 0010 0011100011 xxxxxx 00000000111 1 tap controller state diagram 1 0 test-logic- reset run-test/ idle select- dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select- ir-scan 1 1 1 1 0 0 0 0 00 0 0 00 1 1 1 1 1 1 1 0 00 0 1 1 1 1 0 note: the value adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck. no matter what the original state of the controller, it will enter test-logic-reset when tms is held high for at least five rising edges of tck.
hm62g18512a series 22 package dimensions hm62g18512abp series (bp-119c) hitachi code jedec eiaj mass bp-119c 1.0 g unit: mm a 0.20 4 14.00 13.00 1.27 1.27 22.00 13.88 c c 0.35 0.30 119 0.88 0.06 cab m f f 0.15 c m f c 0.20 a 1 2 3 4 5 6 7 b c d e f g h j k l m n p r t u y 0.69 0.08 2.02 0.22 (0.15) details of the part y b
hm62g18512a series 23 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 2001. all rights reserved. printed in japan. hitachi asia ltd. hitachi tower 16 collyer quay #20-00 singapore 049318 tel : <65>-538-6533/538-8577 fax : <65>-538-6933/538-3877 url : http://semiconductor.hitachi.com.sg url http://www.hitachisemiconductor.com/ hitachi asia ltd. (taipei branch office) 4/f, no. 167, tun hwa north road hung-kuo building taipei (105), taiwan tel : <886>-(2)-2718-3666 fax : <886>-(2)-2718-8180 telex : 23222 has-tp url : http://www.hitachi.com.tw hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel : <852>-(2)-735-9218 fax : <852>-(2)-730-0281 url : http://semiconductor.hitachi.com.hk hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen postfach 201,d-85619 feldkirchen germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi europe ltd. electronic components group whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 585200 hitachi semiconductor (america) inc. 179 east tasman drive san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to: colophon 5.0

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